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SYSTEM-ON-CHIP TEST ARCHITECTURES, VOLUME .: NANOMETER By Laung-terng Mint
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eBay item number:186435498026
Item specifics
- Condition
- Like New
- Seller Notes
- ISBN-10
- 012373973X
- Book Title
- System-on-Chip Test Architectures, Volume .: Nanometer Design for
- ISBN
- 9780123739735
- Subject Area
- Computers, Technology & Engineering
- Publication Name
- System-On-Chip Test Architectures : Nanometer Design for Testability
- Item Length
- 9.3 in
- Publisher
- Elsevier Science & Technology
- Subject
- Systems Architecture / General, Industrial Design / Product, Electronics / Circuits / Vlsi & Ulsi, Electrical
- Publication Year
- 2008
- Series
- Systems on Silicon Ser.
- Type
- Textbook
- Format
- Hardcover
- Language
- English
- Item Height
- 0.6 in
- Item Width
- 7.5 in
- Item Weight
- 55.8 Oz
- Number of Pages
- 896 Pages
About this product
Product Information
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.
Product Identifiers
Publisher
Elsevier Science & Technology
ISBN-10
012373973x
ISBN-13
9780123739735
eBay Product ID (ePID)
15038261281
Product Key Features
Publication Name
System-On-Chip Test Architectures : Nanometer Design for Testability
Format
Hardcover
Language
English
Subject
Systems Architecture / General, Industrial Design / Product, Electronics / Circuits / Vlsi & Ulsi, Electrical
Publication Year
2008
Series
Systems on Silicon Ser.
Type
Textbook
Subject Area
Computers, Technology & Engineering
Number of Pages
896 Pages
Dimensions
Item Length
9.3 in
Item Height
0.6 in
Item Width
7.5 in
Item Weight
55.8 Oz
Additional Product Features
LCCN
2007-023373
Series Volume Number
Volume .
Lc Classification Number
Tk7895.E42s978 2007
Volume Number
Volume .
Table of Content
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
Copyright Date
2008
Target Audience
Scholarly & Professional
Dewey Decimal
621.39/5
Dewey Edition
22
Illustrated
Yes
Item description from the seller
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eBay item number:186435498026
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